Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on

"This Master's thesis outlines the design of a completely asynchronous Field Programmable Gate Array (FPGA) for implementing NULL Convention Logic (NCL) digital

"This Master's thesis is intended to familiarize the reader with the asynchronous delay-insensitive NULL convention Logic (NCL) paradigm and illustrate the desi

Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circ

Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on