A High-Speed Sample-and-Hold Technique Using a Miller Hold Capacitance

Download or read book A High-Speed Sample-and-Hold Technique Using a Miller Hold Capacitance written by Peter J. Lim and published by . This book was released on 1990 with total page 3 pages. Available in PDF, EPUB and Kindle. Book excerpt: The highest bandwidth signal that can be digitized by an analog-to-digital converter is often governed by the performance of a preceding sample-and-hold circuit. Open-loop sample-and-hold topologies generally provide the fastest implementations of the sampling function. However, the precision obtainable with such configurations is typically much lower than can be achieved with alternative closed-loop architectures. In designs where an MOS transistor is used as the sampling switch, input-dependent charge injection associated with the fast turn-off of the switch is often the principal source of sampling error. This charge injection introduces a pedestal error in the hold mode that results in both nonlinearity and gain error. Moreover, the pedestal error is not well-controlled and is therefore difficult to compensate for using self-calibration techniques. This paper introduces a technique for increasing the precision of open-loop sample-and-hold circuits without significantly reducing their sampling rate. With this technique, the sampling error resulting from input-dependent charge injection in the sampling switch is significantly attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the hodl mode through the use of Miller feedback. Reprints. (r.h.).